ASIC Physical design FCL Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences – from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

SMTS SILICON DESIGN ENGINEER (AECG ASIC PD FCL Lead)

THE ROLE: 

We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

THE PERSON:

Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

KEY RESPONSIBLITIES:

• Handling SOC floorplanning/Partitioning, Die size estimation
• Experience on abutted and non-abutted designs

• Handling of Hierarchical designs (Subfcs), Block partitioning, block pin placement, Feedthrough punching, HFN implementation

• Planning clock Mesh/Tree at SOC/Sub System level

• Full SOC bump planning including GPIO Bump Placement, Pad ring generation/GPIO placement, Hard IP bump placement, GPIO and PG RDL routing

• Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
• Provide technical support to other teams 

PREFERRED EXPERIENCE:

• 12+ years of professional experience in physical design, preferably ASIC designs.
• Knowledge on bump placement/critical IP placement.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
• Strong analytical/problem solving skills and pronounced attention to details

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-BM2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.