EMIR engineer

Role Overview:We are seeking a highly experiencedEMIR Lead Engineerto drivepower integrity, IR drop, and electromigration analysisfor advanced SoC designs. The ideal candidate will have strong expertise inEMIR sign-off methodology,PDN planning, andchip-package co-design, along with the ability to lead and mentor a team of engineers.Key Responsibilities:Lead ...

Role Overview:We are seeking a highly experiencedEMIR Lead Engineerto drivepower integrity, IR drop, and electromigration analysisfor advanced SoC designs. The ideal candidate will have strong expertise inEMIR sign-off methodology,PDN planning, andchip-package co-design, along with the ability to lead and mentor a team of engineers.Key Responsibilities:Lead ...

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profileExperienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and...

Responsibilities -Works with top Semiconductor companies for solving Power/Signal/Reliability challenges across Chip-Package-System.Works on RedHawk and RedHawk-SC to help users and to perform EMIR/power-integrity sign-off analysis.Provides expert guidance / consultation to Customers around the globe for solving design challenges.Job Description -Bachelor's...

Mirafra Technologies Hiring PDN / EMIR Engineers:Experience- 3 to 10 yearsNotice period - 0 to 30 daysLocation - BangaloreRoles and Responsibilities: In your new role you will:• Design and develop Flows for IR and EM technology-based solutions for ASIC designs, focusing on signal integrity, power integrity, and thermal management.• Collaborate with...

Key ResponsiblitiesDrive full chip IR/EM convergence on multiple ASICs across different technology nodes.Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design.Work with RTL and PD team in coming up with the low power and UPF specification for the SoC.Work closely with CAD team to come up...

Were Hiring: Physical Design EngineerLocation: Bangalore, IndiaExperience: 5+ YearsKey Responsibilities: Create IO Ring and RDL routing Perform Clock Tree Synthesis (CTS) using Cadence Innovus Conduct EMIR analysis with Ansys Redhawk Execute Physical Verification using CalibreRequirements: Strong understanding of physical design flow & methodologies...

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware...

PDK Physical Verification engineerLocation: BangaloreJob Description:8+ years of DRC/LVS development and support experience required. Exceptions made for the right candidates.Good knowledge of CMOS fundamentals with background in electrical engineering or semiconductor physicsGood basic understanding of DRC, LVS and Parasitic Extraction ,Knowledge of Calibre...

Company DescriptionChiplogic Technologies, established in 2018, is an IP and Product Engineering Services company. We specialize in providing high quality and dependable services in semiconductor, systems, IoT, and AI/ML areas. Our services include turnkey semiconductor design and system solutions from concept to silicon, as well as IoT final system...