Senior Formal Verification Engineer

4 days ago

Bengaluru, Karnataka, India Careernet Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Key Skills: Formal Verification, Frontend Verification, Functional Verification

Roles and Responsibilities:

  • Develop detailed formal verification (FV) test plans based on design specifications.
  • Collaborate with design teams to refine micro-architecture specifications.
  • Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.
  • Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.
  • Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.
  • Develop and maintain scripts to enhance FV productivity and streamline verification processes.
  • Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.
  • Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback.
  • Strong proficiency in System Verilog/Verilog.
  • Good scripting abilities with Python or Perl.

Skills Required:

  • Strong experience in Frontend Verification, Formal Verification, and Functional Verification
  • Good understanding of System Verilog, Verilog, and UVM
  • Knowledge of Assertion-Based Verification techniques
  • Scripting skills in Python or Perl
  • Experience with EDA tools used for formal verification

Education: Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field.

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