Analog IP Design Lead

About Tata Electronics Private Limited:Tata Electronics Pvt. Ltd. is a prominent global player in the electronics manufacturing industry, with fast-emerging capabilities in Electronics Manufacturing Services, Semiconductor Assembly & Test, Semiconductor Foundry, and Design Services. Established in 2020 as a greenfield venture of the Tata Group, the company aims to serve global customers through integrated offerings across a trusted electronics and semiconductor value chain.

With a rapidly growing workforce, the company currently employs over 65,000 people and has significant operations in Gujarat, Assam, Tamil Nadu, and Karnataka, India. Tata Electronics is committed to creating a socioeconomic footprint by employing many women in its workforce and actively supporting local communities through initiatives in environment, education, healthcare, sports and livelihood. Job Description: Seeking for highly skilled Analog IP Design Lead to join the TATA Electronics Business Unit where in the candidate will get to work on a wide range of exciting products and foundry enablement.

The successful candidate will work with 100% quality and with efficiency with quick time to market mindset. This role requires working closely with the internal IP design, TD, PDK, Layout, test and product engineering teams. The roles and responsibilities will include the working with customer requirement, architecture, circuit design, simulations and verification and all the interface of the memory design like amplifier, multi read/write decoders etc.

Functional Requirements: Requires MTech in Electrical (VLSI, Microelectronics) from a reputed university with 10-15 years of in field experience Candidate with any of the below mentioned Analog IP design experiences can apply. Experienced in one or more aspects of Analog circuit design from block level to full chip with a demonstrated history in driving design innovation and best practices. Must be proficient in transistor level design and system implementation of typical building blocks like charge pumps, comparators, amplifiers, bandgaps, linear regulators, switching regulators, TX, RX, Drivers, Interpolators etc.

Candidates with solid Analog circuit design concepts and have worked to design, develop and deliver on quality collaterals of IP may apply for this job Role. Candidates with knowledge to design as many of the IPs like GPIO, PLL, LDO, Oscillators, DLL, X-tal Oscilators, DC-DC Buck, ADC/DAC may please apply. Candidates with knowledge to Arch design and develop DC-DC- Buck/Boost, SerDes, DDR will have advantage.

What You will be doing: Supervision of overall Analog IP development. Architecture development, decision making in circuit topology finalization, review of functional and performance of all Analog IPs.

Hands-on Capability and design of complex IPs Interface with layout, verification, test, product and application engineers to successfully bring new products from initial concept through release to production Participate in discussions and draft documents of technical issues and other design aspects with internal teams and customers Instigate regular peer reviews with other Analog engineers Guide the layout of circuit blocks for high-speed performance and precision operations Drive IP Architecture, Specification and enable IP vendors for IP design and delivery Interface with Customer for respective IP requirement and Development Run block-level and top-level mixed-mode simulations to meet datasheet parameters Lab evaluation and support for circuit blocks/whole ICs Support test development and ramp to production Qualifications: Masters &/ Ph. D in Electrical & Electronics Engineering or Microelectronics.10-15 years in Analog Circuit Design, Simulation and Verification. Solid understanding of IC processing, ranging from 130nm, 110nm, 90nm, 40nm, 22nm. Ability to work with Package Design team to provide inputs on Signal routing and conducting SI simulations.

Schematic generation, simulation and verification using Analog Design EDA tools (Cadences / Synopsys) Familiarity with complete simulation suite including block level, top-level, worst-case corner identification and Monte Carlo analysis along with parasitic extraction and simulation. Solid understanding of layout care-about and identifying limitations of design for testability, debug, characterization and production/yield targets. Generation of IP Collaterals adhering to Industry standards – IP Datasheets, LEF, LIB, Simulations Models, AMS-Models for SOC integration and support verification.