Staff, Design Verification

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We're building high-performance RISC-V CPUs from the ground up, and we need someone who can help us test them thoroughly and thoughtfully. As a testbench lead, you'll design and maintain the infrastructure that makes sure our cores behave exactly as intended. If you enjoy figuring out how things break (and fixing them), building clean and reusable systems, and working with a team that values both rigor and creativity, we'd love to talk.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You've built and maintained testbenches for CPU cores or similar designs, using SystemVerilog, UVM, and C++.
• You like creating clean, reusable components — from transactors to functional models — that others can plug in and build on.
• You're comfortable working across both software-style C++/UVM environments and hardware-style simulation flows.
• You enjoy collaborating with design teams and helping them debug issues quickly and clearly.

What We Need

• Someone to design and grow a UVM testbench setup that works for both block-level and full-chip simulation.
• The ability to write C++ code that fits into a DV framework — and help shape that framework as it evolves.
• A good understanding of CPU microarchitecture and how to test it effectively.
• Comfort working across tools, from open-source simulators like Verilator to commercial environments and emulators.

What You Will Learn

• How to design testbenches that scale with complexity — and keep them maintainable as the chip grows.
• How to support both simulation and emulation from the same DV infrastructure.
• How custom C++ and UVM environments can coexist to improve verification workflows.
• How different teams — RTL, DV, software, tools etc — come together to build AI-focused silicon.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.