Rtl Design Engineer

4 days ago

Bengaluru, Karnataka, India Capgemini Full time ₹ 9,00,000 - ₹ 12,00,000 per year

Job Description for RTL

We are hiring a SoC Integration Engineer with strong expertise in RTL coding and SoC integration flows. The ideal candidate should have hands-on experience with SpyGlass Lint, CDC, DC Synthesis, and VCLSP, along with scripting knowledge.

Key Responsibilities:

  • Integrate IP blocks into SoC at RTL level
  • Perform RTL coding and micro-architecture design (Verilog/VHDL)
  • Run and debug SpyGlass Lint, CDC, and DC Synthesis flows
  • Conduct STA and design rule checks
  • Develop automation scripts (Perl, Python, Shell, Tcl)
  • Collaborate with verification and physical design teams
  • Work on VCLSP and SoC-level integration flows

Primary Skills:

  • RTL Design: Verilog, VHDL, Micro-architecture
  • Tools: SpyGlass Lint, CDC, DC Synthesis, STA
  • SoC Integration: IP development, VCLSP
  • Scripting: Perl, Python, Shell, Tcl

Secondary Skills:

  • Tool Flows: Synopsys, Cadence
  • Processors & Protocols: ARM Cortex, DMA, DDR, SPI, I2C, UART
  • Bus Interfaces: AHB, AXI, APB
  • High-Speed Interfaces: Ethernet, USB, PCIe
  • Multimedia Interfaces: MIPI CSI/DSI
  • Memory Interfaces: LPDDR

Qualification:

  • Bachelors or master's degree in electrical engineering, Computer Engineering, VLSI, or a related field.

Note: For RTL Don't ADD FPGA profiles.

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