Lead IP

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
SMTS SILICON DESIGN ENGINEER
The Role
As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

The Person
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBILITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Proficient in IP, SoC level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Desirable experience with prior exposure on SoC/NoC Interconnects, High-Speed protocols like PCIe, USB3
• Experience in SoC Peformance verification or Performance modeling is a strong plus
• Experience in DFx logic verification is a strong plus
• Experience in Crypto IP verifiation at SoC level is a plus
• Desired experience in DDR memory controller verification.
• Exposure to Synopsys VCS, Verdi tool features to aid in Code coverage, Fault coverage analysis is a plus.
• Excellent debugging skills in RTL and 0'delay Gate-level-simulations
• Scripting language experience: Perl, Python, Makefile, shell preferred
• Experience in SoC verification and usecases is a plus.

Good understanding and hands-on experience in the UVM concepts and SystemVerilog language

• Exposure to leadership or mentorship in leading teams is asset

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described:
AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.