Analog layout Engineer

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.• Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.• Responsible for on-time delivery of block-level...

Role & responsibilitiesResponsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.Responsible for on-time delivery of...

Principal Analog & Mixed Signal Layout EngineerWe Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and...

Company Description:MosChip Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with over 1300 engineers in Silicon Valley, USA, and India. Our engineering solutions include end-to-end silicon design, verification, systems, software, and device engineering, along with multimedia, mobility, connectivity, AI/ML...

Analog LayoutLocation: Bangalore / HyderabadJob Description:TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.Verification flows –...

We are looking For Analog Layout EngineerSkills: who worked on Lower nodes 3nm, 5 nm, 7 nm, 10 nmExp: 4-9yrsLoc: HYD

We're hiring Analog Layout Engineers (3–7 years) with hands-on experience in lower technology nodes, layout design, and DRC/LVS verification. Location: Hyderabad. Immediate joiners preferred.

i)Analog Layout EngineerSkills: who worked on Lower nodes 3nm, 5 nm, 7 nm, 10 nmExp: 4-9yrsLoc: HYDii) Skills: Non intel ExpExp:6+yrsLoc: BLRiii)Skills: finfet nodesExp:8+yrsLoc: BLR

Must have 3-5 of experience instandard cell layout, analog, mixed-signal and custom digital blockdesigns in advanced CMOS process. Should have expertise inmultiple standard cell layout library developments. Should be ableto perform standard

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and...