Staff High-Speed Interface PHY IP Digital Design Engineer
1 week ago
Key Skills: Lint, RTL Design, CDC, MIPI, PCIe, Serdes
Roles and Responsibilities:
- Implement front-end RTL design for SERDES high-speed interface PHYs.
- Ensure RTL linting compliance, CDC correctness, low-power rules (UPF), and DFT readiness.
- Collaborate with the functional verification team on test-plan development, simulations, and debugging.
- Develop timing constraints and deliver synthesized netlists to the physical design team, supporting PD STA activities.
- Write UPF files, perform power-aware equivalence checks, and conduct low-power verification.
- Insert DFT logic and perform ATPG analysis for SAF and TDF coverage.
- Support SoC integration and contribute to pre- and post-silicon chip-level debugging.
- Work effectively in global teams, demonstrating strong communication and documentation skills.
- Drive quality and reliability standards in RTL design to meet project timelines and industry compliance.
Skills Required:
- Strong RTL design expertise with Lint and CDC experience
- Knowledge of low-power design (UPF, equivalence checking)
- Experience with DFT insertion and ATPG coverage analysis
- Familiarity with SERDES, MIPI, PCIe protocols
- Ability to collaborate with verification and physical design teams
- Strong analytical, debugging, and problem-solving skills
Education:
- M.Tech/B.Tech in Electrical Engineering or Computer Science
- Minimum of 8 years of hardware engineering experience
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