RTL Micro-Architecture Design Engineer DRAM Controller_TB5-TB7_DRAM_Memory

11 hours ago

SSIR Goldstone Bangalore India Samsung Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Position Summary

Role and Responsibilities

5 to 14 years of work experience in VLSI RTL IP or Subsystem design

Job Description/background:

· Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property. 

Design and Engage with other architects within the IP level to drive the Micro-Architectural definition.

· Deliver quality micro-architectural level documentation.

· Produce quality RTL on schedule by meeting PPA goals.

· Be responsible for the logic design/ RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. 

· Collaborate with the verification team to ensure implementation meets architectural intent. 

· Hands-on in running quality checks such as Lint, CDC and Constraint development.

· Substantial background in debugging designs in the simulation environments. 

· Deep understanding of fundamental concepts of digital design 

 Preferred Skill: 

· Strong Verilog/System Verilog RTL coding skills. 

· Experience with DRAM Memory Conytroller design.

· Knowledge of DRAM standard (DDR4/5) memory.

· Interface/Protocol experience required - AHB/AXI, Processor local bus, Flash, SPI, UART, etc.·

· Experience with Xilinx/Intel FPGA Tool flow

· Knowledge of PCIe/PIPE

· Knowledge of projects with (Microblaze, ARM cores, etc.)

· Knowledge of CXL Protocol is appreciated.

Skills and Qualifications

    Master's degree or Bachelor's degree in Electronics or Electrical Engineering.

· to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure. 

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