Senior EDA Engineer

18 hours ago

Bengaluru, Karnataka, India CareerFit Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Position Title: Senior EDA Engineer Cadence Virtuoso, SKILL/CDF, Tool Integration

Role Overview:

We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform.

Key Responsibilities:

  • Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools.
  • Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks.
  • Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries.
  • Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information.
  • Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA.
  • Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools.
  • Troubleshoot issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups.
  • Document technical processes, create reusable automation scripts, and contribute to team best practices.
  • Collaborate with AI and software teams to integrate EDA tools into Maieutics AI co-pilot platform and support continuous improvement of design automation.

Required Skills & Experience:

  • 3+ years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows.
  • Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments.
  • Proven experience managing and customizing CDF files for parametric device libraries in Cadence.
  • Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data.
  • Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks.
  • Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python).
  • Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout).
  • Strong UNIX/Linux command-line skills and scripting abilities.
  • Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent).
  • Excellent communication skills and ability to operate effectively in a startup team environment.

Preferred Qualifications:

  • Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains.
  • Experience with Spectre, ADE simulation, and analog verification flows.
  • Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design.
  • Familiarity with AI/ML integration in design tools is a plus.

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