DV Coresight_JTAG

Job Requirements

We are seeking a skilled and experienced Hardware/Firmware Engineer with a specialization in debug and trace architectures, particularly focused on Arm CoreSight and JTAG. In this critical role, you will be a key player in the development, integration, and validation of our advanced System-on-a-Chip (SoC) products. Your expertise will be vital in creating the on-chip infrastructure that enables efficient hardware and software debugging, system-level analysis, and product bring-up.

This position requires a unique blend of hardware design, low-level software/firmware development, and a deep understanding of complex debug protocols.

• Architect and Design Debug Systems: Contribute to the architectural definition and implementation of the debug and trace infrastructure for our next-generation SoCs, using Arm CoreSight components (e.g., DAP, ETM, PTM, ETB, TPIU, CTI) and related protocols.
• JTAG & Boundary Scan Development: Design, verify, and validate the JTAG (IEEE Test Access Port (TAP) and boundary scan chains. Ensure proper configuration and functionality for manufacturing test, board-level debug, and in-system programming.
• System-Level Integration & Verification: Integrate debug and trace IP with the main SoC fabric, ensuring correct connectivity, clocking, and power domain interactions. Develop and execute comprehensive pre-silicon verification test plans.
• Firmware & Software Debug Support: Develop low-level firmware and scripts for debug features, including initializing the CoreSight components, managing JTAG communication, and enabling debug functionality for software teams.
• Silicon Bring-up & Debug: Be a primary point of contact for silicon bring-up. Use external debug probes (e.g., J-Link, Lauterbach TRACE32) to debug complex hardware and software issues on new silicon, including processor hangs, unexpected resets, and corrupted memory.
• Protocol Expertise: Apply a deep understanding of standard debug protocols and interfaces like Arm Debug Interface (ADI), Serial Wire Debug (SWD), and the AMBA bus protocols (APB, AXI).
• Tooling & Automation: Create and maintain scripts (Python, Perl, TCL) to automate test flows, generate configuration files, and support the debug and validation process.
• Documentation: Create detailed documentation for the debug and trace architecture, including programmer's guides, user manuals, and technical specifications for internal and external customers.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• [Number] years of experience in hardware or firmware engineering, with a focus on debug and trace.
• Proven, hands-on experience with Arm CoreSight architecture and its components.
• In-depth knowledge of the JTAG (IEEE standard and its application for debug and test.
• Proficiency in hardware description languages (Verilog, SystemVerilog) and experience with verification methodologies (UVM is a plus).
• Strong programming and scripting skills (Python, C/C++, Perl, TCL).
• Experience with embedded systems, processors (Arm Cortex-A/R/M), and low-level firmware.
• Familiarity with industry-standard debug tools and probes.
• Excellent analytical, problem-solving, and debugging skills.
• Strong communication and collaboration skills to work with cross-functional teams (design, verification, software, and test).

• Experience with other debug architectures (e.g., MIPS EJTAG, Intel DTS).
• Knowledge of Design for Testability (DFT) concepts, including scan chains and Built-in Self-Test (BIST).
• Familiarity with trace data analysis and performance monitoring.
• Experience in the bring-up of first-pass silicon.
• Knowledge of security protocols and secure debug.