Senior Design Verification Engineer- Lead and above

5 days ago

Bengaluru Hyderabad, India Tessolve Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Position: Sr.Design Verification Engineer-Lead and above

Experience: 5+ years to 30 years

Location - Bangalore/Hyderabad

Notice period: immediate to 30 days most preferable.

Position Description:

  • To be part of a highly skilled ASIC Team working on the newest technology nodes
  • Responsible for overall IP verification from test plan creation, UVM development to signoff.
  • Pair with similar domain specialists across other geographical locations on core technical initiatives

SKILLS required:

  • Good knowledge of System Verilog TB, UVM Methodology, Debug and VIP Development
  • Exposure of SERDES/UNIPRO/PCIE/UFS/DDR protocols is an advantage
  • Exposure to verification of complex high speed PHY
  • Proven track record of building testplan, UVM environment and testbenches
  • Experience with RTL debugging, ScoreBoarding and Code Coverage Analysis
  • The position requires good written & verbal communication skills
  • Strong commitment and ability to work in cross functional and globally dispersed teams

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