Staff Engineer Verification

7 days ago

Bengaluru, Karnataka, India Infineon Full time ₹ 15,000 - ₹ 28,00,000 per year

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General information

WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game changing solutions for green and efficient energy, clean and safe mobility, as well as smart and

secure IoT. Together, we drive innovation and customer success, while caring for our people and

empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in?

We are on a journey to create the best Infineon for everyone.

This means we embrace diversity and inclusion and welcome everyone for who they are. At

Infineon, we offer a working environment characterized by trust, openness, respect and tolerance

and are committed to give all applicants and employees equal opportunities. We base our

recruiting decisions on the applicants experience and skills.

Please let your recruiter know if they need to pay special attention to something in order

Job Description

In your new role you will:

  • Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices.
  • Designing self-checking test benches using modern verification techniques
  • Implementing functional coverage and assertions using System Verilog and UVM.
  • Developing TB environment using SV and UVM.
  • Developing test and functional coverage plans based on device specifications.
  • Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes.

Your Profile

You are best equipped for this task if you have:

  • Engineering in Electrical/electronic streams, or equivalent experience.
  • 7+ years experience in constrained-random, coverage driven verification environments.
  • Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology).
  • Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues.
  • A solid understanding of verification concepts and experience designing class-based test benches.
  • C coding, Formal verification methods and Power aware simulation will be an advantage
  • Excellent written and oral communication skills
  • Strong debugging skills, functional simulations and GLS simulations

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