Technical Manager

2 weeks ago

Bengaluru, Karnataka, India b1793b15-fd6d-4f70-a9bf-511d669d2106 Full time ₹ 12,00,000 - ₹ 36,00,000 per year

About the Role:

We are seeking an experienced 
Analog

Layout

Manager

to lead a team of 

layout

engineers in the design and delivery of high-performance 

analog

and mixed-signal IPs in advanced process nodes
(7nm and below

). The ideal candidate will have hands-on experience in 

analog

custom 

layout

, strong expertise in SERDES 

layout

, and a proven track record of technical leadership and project execution.

Key Responsibilities:

  • Lead and manage a team of 
    analog
     
    layout
     engineers working on complex IP blocks such as SERDES, PLLs, ADCs/DACs, LDOs, and other mixed-signal components.
  • Drive 
    layout
     development from floorplanning through signoff, ensuring adherence to design requirements, foundry rules, and schedule.
  • Own 
    layout
     reviews, quality checks (DRC/LVS/ERC), and provide guidance on 
    layout
     best practices.
  • Collaborate closely with circuit designers, digital/
    analog
     integration, verification, and physical design teams.
  • Work on advanced technology nodes (7nm and below), applying knowledge of FinFET 
    layout
     challenges, EM/IR, and process variations.
  • Mentor junior 
    layout
     engineers, define 
    layout
     methodologies, and improve 
    layout
     efficiency and quality.
  • Manage project schedules, resource planning, and cross-site coordination to ensure timely delivery.

Required Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering or a related field.
  • 10+ years of hands-on 
    analog
     
    layout
     experience.
  • Deep expertise in lower node 
    layout
     (7nm, 5nm, or below), including understanding of double patterning, 
    layout
    -dependent effects, and reliability concerns.
  • Proven experience with high-speed SERDES 
    layout
     (multi-Gbps), including clock/data paths, shielding, matching, and isolation techniques.
  • Strong skills in EDA tools (Virtuoso, Calibre, IC Compiler, etc.).
  • Experience with leading 
    layout
     reviews, debugging LVS/DRC issues, and delivering high-quality GDS for tapeout.
  • Excellent communication, collaboration, and leadership skills.

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