Sr. SOC level verification
2 days ago
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SENIOR SILICON DESIGN ENGINEER
THE ROLE (SOC Verification Engineer: GDP DV ):
Work on SOC level verification activities for GDP (PCIE,USB,Ethernet,I2C,I3C,Uart,SPI) and subsystem or signature IP's in the complex SOC. He will be responsible for verifying and integration.Add on responsibility SOC Integration after having co-ordination with IPs, SOC (Design, DFT & PD) teams. To take complete IP integration responsibility, including the deployment verification.Understand spec, interact with customer, team members, lead and come up with testplan, code testcases, checkers, UVM agents, scoreboards and assertions.THE PERSON:
Engineer with strong self-driving ability.Need excellent communication skills (both written and oral)Strong problem-solving skills, go to person for UVM coding, Testcase coding, checkers and assertions.KEY RESPONSIBILITIES:
Understanding Ips like (PCIE,USB,Ethernet,I2C,I3C,UART,SPI)IP deployment to complex SOCs and get the integration testing done. Testcase coding, Debugging issues, regressions, UVM agent coding, checkers coding, scoreboard coding and Assertions coding.PREFERRED EXPERIENCE:
Knowledge of High speed peripheral (PCIE,USB,Ethernet) and Low speed peripherals (I2C,I3C,UART,SPI)Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification toolsStrong hands-on experience in different SOC Verification activities, UVM, System Verilog, kv, X86, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc.Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.JIRA based project management is a plus.ACADEMIC CREDENTIALS:
BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE~5-10 years of strong DV experience in IP, Sub System & SOC Verification, IP deployment/integration.#LI-SR4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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