Design Verification Engineer
3 days ago
Position:
Design Verification Engineer
Experience:
4+ Years
Location:
Remote – India
About the Role
We're seeking
top-tier Design Verification Engineers
to join our silicon engineering team. You'll work on the
full chip verification lifecycle
—from test planning and environment setup to debug and closure—using industry-standard methodologies.
Key Responsibilities
- Own and execute
full-chip verification
activities. - Develop and maintain
SystemVerilog/UVM or Specman/E
testbenches. - Create verification environments, components, and reusable libraries.
- Perform
test planning, coverage analysis
, and debug RTL with designers. - Work collaboratively with design and architecture teams to ensure functional correctness.
- Drive verification closure with high coverage and quality standards.
Requirements
- 4+ years of hands-on
chip or SoC verification
experience. - Strong expertise in
SystemVerilog/UVM
or
Specman/e
. - Deep understanding of
RTL design and simulation tools
. - Proven experience in
debugging complex SoCs
. - Solid grasp of
functional coverage, assertions, and constrained random testing
.
Preferred Skills
- Experience with
large SoC or ASIC full-chip environments
. - Exposure to
verification automation frameworks
. - Excellent analytical, debugging, and communication skills.
-
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