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FPGA Silicon Design Verification Engineer

2 weeks ago

Bengaluru, Karnataka, India Altera Full time US$ 1,25,000 - US$ 1,75,000 per year

Job Description:

Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

  • Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
  • Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
  • Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
  • Run IO PHY tests with AMS (Digital/Analog Mixed Signal Simulation).
  • Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
  • Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
  • Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

Qualifications

  • Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.
  • Related technical experience should be in/with: Pre Silicon Validation/Verification.
  • JESD 79-5 DDR5, JESD209-5 LPDDR5, JESD 209-4 LPDDR4, DDR PHY Interface (DFI 5.1)
  • Tessent SSN scan
  • OVM/UVM, System Verilog, constrained random verification methodologies.