STA & Synthesis Engineer
2 weeks ago
Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions.
Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure.
Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.
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STA & Synthesis Engineer
3 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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STA & Synthesis Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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STA & Synthesis Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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Sta & Synthesis Engineer
3 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. - Netlist and constraint sign in checks and validation. - Responsible to complete synthesis till final-opt with DFT insertion - Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low...
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RTL Synthesis and STA
6 days ago
Bengaluru, Hyderabad, India Acesoft Labs Full time ₹ 6,00,000 - ₹ 18,00,000 per yearDear Candidate,We are hiring for our esteemed client for the role STA & Synthesis Engineer.Exp - 3+ YearsNP - Immediate to 15 DaysLocation - Bangalore, Hyd (WFO)JD -Synthesis & STA Engineers:Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing...
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STA & Synthesis Engineer
3 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...
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STA & Synthesis Engineer
3 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...
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STA & Synthesis Engineer
2 weeks ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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Sta & synthesis engineer
1 week ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...
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STA & Synthesis Engineer
7 days ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
