Lead Design Verification Engineer

3 days ago

Bangalore Rural Bengaluru, India Sykatiya Technologies Full time ₹ 15,00,000 - ₹ 20,00,000 per year

Role & responsibilities

Key Responsibilities:

  • Develop and execute test plans for high-speed protocols such as PCI, PCIe (Gen1 to Gen5), USB (2.0/3.0), Ethernet (10/100/1G/10G), and MAC.
  • Write and maintain SystemVerilog/UVM testbenches for functional verification.
  • Collaborate with design teams to understand architecture and develop verification strategies.
  • Debug RTL issues, analyze simulation failures, and provide comprehensive bug reports.
  • Perform coverage analysis (code and functional) and drive coverage closure.
  • Integrate VIPs (Verification IPs) and ensure compliance with industry standard protocol specifications.
  • Work on assertions, checkers, and monitor development for protocol features.
  • Participate in design and verification reviews, and contribute to continuous improvement.

Required Skills:

  • Strong expertise in SystemVerilog, UVM methodologies.
  • Solid understanding of PCIe, USB, Ethernet/MAC protocols.
  • Experience in testbench architecture, test planning, and constrained-random verification.
  • Knowledge of debugging tools like SimVision, Verdi, or similar.
  • Exposure to protocol compliance testing and formal verification is a plus.
  • Experience with scripting languages (Python, Perl, Tcl, Shell) for automation.

Preferred candidate profile

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