Silicon Engineer, PD

Multiple Locations, India

Date posted

Oct 15, 2025

Job number

1896672

Work site

3 days / week in-office

Travel

0-25%

Role type

Individual Contributor

Profession

Hardware Engineering

Discipline

Silicon Engineering

Employment type

Full-Time

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft's Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Sr. Physical Design Engineer to join the team.

• BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
• Min 8+ years of experience in semiconductor design.
• Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
• Expertise in timing analysis, timing ECOs strategies and timing signoff is MUST.
• Hands-on experience of Fullchip/Subsystem level timing analysis with inter-partition timing analysis across multiple scenarios modes (FUNC/DFT) & corners, timing ECOs (hierarchical timing ECOs), reviewing & solving PrimeTime logfile Errors/Warnings, various quality/pre-requisite checks is a MUST.

Preferred:

• Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes.

• Hands-on experience of Fullchip/Subsystem level timing analysis with inter-partition timing analysis across multiple scenarios modes (FUNC/DFT) & corners, timing ECOs (hierarchical timing ECOs), reviewing & solving PrimeTime logfile Errors/Warnings, various quality/pre-requisite checks is a MUST.

• Strong understanding of constraints generation, STA, timing optimization, and timing closure.
• Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
• Hands-on experience in power analysis (using PrimePower, PT-PX) and low power optimization methodology.
• Experience with IO/Bump planning, RDL routing will be a big-plus.
• Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise.
• Experience in EDA tools such as Fusion Compiler, Primetime, StarRC, RedHawk, Formality, etc.
• Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus
• Strong problem-solving and data analysis skills, complemented by advanced scripting capabilities in Perl, TCL, Python.

In this high impact role, you will be responsible to:

• Own execution from synthesis to place and route of partitions through floorplanning for optimizing blocks for Power, Performance and Area, develop and implement robust clock distribution strategies that meet design specifications.
• Converge the design through all signoff aspects viz., timing, EMIR, physical/layout fixes, formal equivalence verification, low power verification and all signoff and paranoia checks.
• Own Timing analysis and convergence of at Subsystem/SubChip level. Triage, analyze inter-partition timing and collaborate and coordinate with respective block owners to provide feedback (clock latency, IO budgeting, optimization, clock skewing etc.,) to fix both internal and interface timing violations across all functional and DFT modes.
• Own and drive Hierarchical Timing ECOs at Subsystem/Subchip level and pushdown timing ECOs at top-level and block interfaces (as supported by ECO methodology to enable convergence.
• Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies.
• Coordinate effectively across cross-functional teams such as DFT, RTL/Design/IP, STA, CAD, Architecture, Power & Performance, and both internal and external stakeholders.
• Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.
• Mentor junior engineers on technical issues.
• Provide technical leadership and foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

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Industry leading healthcare

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Educational resources

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Discounts on products and services

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Savings and investments

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Maternity and paternity leave

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Generous time away

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Giving programs

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Opportunities to network and connect

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.