High Performance DSP core Implementation(Synthesis) Senior Lead

6 days ago

Noida, Uttar Pradesh, India Qualcomm Full time ₹ 15,00,000 - ₹ 25,00,000 per year

High Performance DSP core Implementation(Synthesis) Senior Lead Engineer

General Summary:

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Experience:Minimum 4 to 6 years of hands on experience in Synthesis and LEC

Job Role

  • Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
  • Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
  • Experience in all aspects of timing closure for multi-clock domain designs.
  • Should be familiar with MCMM synthesis and optimization.
  • Should have good understanding of low-power design implementation using UPF.
  • Experience with scripting language such as Perl/ Python, TCL.
  • Experience with different power optimization flows or technique such as clock gating.
  • Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
  • Should be able to handle ECOs and formal verification and maintain high quality matrix

Skill Set

  • Proficiency in Python/Tcl
  • Familiar with Synthesis tools (Fusion Compiler/Genus),
  • Fair knowledge in LEC, LP signoff tools
  • Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
  • Familiarity with standard software engineering practices like Version
  • Control, Configuration Management, Regression is a plus
  • Should be sincere, dedicated and willing to take up new challenges

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