DDR Engineer

Job Description: We are looking for DDR Verification Engineers to work on high-performance memory subsystems.Responsibilities:Perform DDR protocol-level verification for SoC designsDevelop SV/UVM-based test environmentsDebug and validate DDR timing and performance complianceEnsure coverage closure for DDR controller and PHY verificationCollaborate with...

Design Verification Engineer - Senior / Lead / Sr. Lead Location: Bangalore / Hyderabad Experience: 4 to 10 Years Required Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of hands-on experience in design verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe....

Design Verification Engineer - Senior / Lead / Sr. LeadLocation: Bangalore / HyderabadExperience: 4 to 10 YearsRequired Qualifications:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.4+ years of hands-on experience in design verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe.Expertise in...

Job DescriptionThe ideal candidate will get to work on Verification of complex Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs.KEY RESPONSIBILITIES:- Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.- Create...

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology Position Description RTL Design Engineer for DDR Memory Controller IP development team The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence All leading DDR memory protocols will be supported -...

DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols.Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM (Universal...

JD:This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies.Key Responsibilities:Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies.Design and implement verification environments using SystemVerilog and UVM methodologies.Develop test cases to validate...

Experience: 5 Years Location: Bangalore/Hyderabad Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics Roles and Responsibilities DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols. Testbench Development: ...

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using SystemVerilog and UVM methodologies. Develop test cases to validate...