Analog Layout Engineer: 7 nm or Lesser with DDR Exp

2 weeks ago

Hyderabad, Telangana, India Cyient Full time US$ 1,50,000 - US$ 2,00,000 per year

Dear Analog Layout Engineers,

We, Cyient Semiconductor is hiring for Sr/ Staff Analog Layout Engineers: 7nm/ Lesser with DDR Exp for Offshore-Onshore Model based Global Product Solution from Scratch.

Exp Range: 5-8 Yrs

Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch

About the Role

We are seeking a highly skilled Analog Mixed-Signal (AMS) Layout Engineer with proven expertise in 7nm or smaller technology nodes, FinFET architecture, and DDR interface layouts. The ideal candidate will work closely with design teams to deliver high-performance, low-power, and area-efficient layouts for cutting-edge semiconductor products.

Key Responsibilities

  • Design and develop full-custom AMS layouts for high-speed and low-power circuits in 7nm or below process nodes.
  • Perform layout design for FinFET devices, ensuring optimal device matching, symmetry, and parasitic control.
  • Implement layout for DDR interfaces (DDR3/DDR4/LPDDR/DDR5) including IOs, PHY blocks, and termination circuits.
  • Conduct layout verification (DRC/LVS/ERC/ANT checks) using industry-standard EDA tools.
  • Collaborate with circuit designers to meet performance, power, and area (PPA) targets.
  • Optimize layouts for signal integrity, IR drop, electromigration, and manufacturability.
  • Participate in design reviews and provide feedback on floorplanning, routing strategies, and parasitic extraction (PEX) results.
  • Ensure compliance with foundry process design kits (PDK) and fabrication guidelines.

Required Skills & Qualifications

  • Bachelors or Master's degree in Electronics, Electrical Engineering, or VLSI Design.
  • 5-8 years of experience in AMS layout engineering.
  • Hands-on experience with 7nm, 5nm, or advanced FinFET nodes in high-volume production.
  • Strong knowledge of DDR interface layouts and signal integrity considerations.
  • Proficiency in Cadence Virtuoso, Mentor Calibre, Synopsys IC Validator, or equivalent tools.
  • Deep understanding of layout techniques for analog, digital, and mixed-signal blocks (e.g., PLLs, SerDes, ADC/DAC, IOs).
  • Experience with power distribution, shielding, and ESD structures.
  • Excellent problem-solving skills.

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