Senior Verification Engineer

5 hours ago

Bengaluru, Karnataka, India StudyMitr Full time ₹ 17,50,000 - ₹ 25,00,000 per year

We are looking for a highly skilled Design Verification Engineer to join our semiconductor R&D team. The ideal candidate must have strong hands-on experience in System Verilog, UVM, and complex IP/SoC verification. You will work on next-generation compute subsystems including CPU/GPU clusters, AI accelerators, high-speed interfaces, memory subsystems, and interconnect fabrics.

Experience Required:

7-8 years
in ASIC / SoC / IP Verification/UVM

Key Responsibilities:

  • Own and execute
    IP / Subsystem / SoC verification
    from planning to coverage closure
  • Develop
    UVM-based testbenches
    , environments, and reusable verification components
  • Write
    test plans
    , implement
    functional coverage
    , drive closure
  • Debug complex failures using waveforms, logs, and architectural understanding
  • Verify industry-standard protocols:
  • PCIe, USB 3.x, Ethernet, MIPI, AXI/CHI, LPDDR/DDR, UFS
  • Collaborate with design, architecture, firmware, and validation teams
  • Provide technical mentorship to junior engineers (for Lead roles)
  • Deliver high-quality verification sign-off for tape-out

Required Qualifications:

  • Strong hands-on expertise in System Verilog
    , including constrained-random stimulus generation, functional coverage, and SVA (System Verilog Assertions).
  • Deep experience with UVM methodology
    , including development of agents, drivers, monitors, scoreboards, sequences, and reusable verification environments.
  • 5–12 years of ASIC/SoC/IP functional verification
    experience with proven ownership of verification planning, testbench architecture, and coverage closure.
  • Protocol verification experience
    in at least one major interface such as PCIe Gen4/5, USB 3.x, Ethernet (1G–25G), LPDDR/DDR/LPDDR5/6, UFS/eMMC, MIPI CSI/DSI, or AXI/CHI/NoC interconnects.
  • Strong debugging skills
    using waveforms, logs, checkers, and scoreboards, with experience in identifying root causes across IP, subsystem, and SoC-level interactions.
  • Hands-on experience with industry-standard verification tools
    , including Synopsys VCS/Verdi, Cadence Xcelium, and Siemens QuestaSim/ModelSim.
  • Solid understanding of digital design fundamentals
    , clocking, resets, FIFOs, state machines, and microarchitecture.
  • Proficiency in scripting languages
    such as Python, Perl, or Shell for automation, regressions, and verification infrastructure improvement.
  • Strong collaboration and communication skills
    , with ability to work closely with RTL design, architecture, and firmware teams; mentoring experience preferred for senior/lead roles.
  • Bachelor's or Master's degree
    in Electronics, Electrical, Computer Engineering, VLSI, or a related discipline, with strong fundamentals in semiconductor design and verification.

Why Join Us?

  • Work on next-gen SoCs powering cutting-edge products
  • Opportunity to own complex subsystems
  • Fast-growing team → strong career growth
  • Competitive salary

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