Physical Design Engineer

Introduction

We are seeking an experienced Physical Design Engineer to join our team developing next-generation AI acceleration SoCs and chiplets at EdgeCortix. In this role, you will play a key part in driving synthesis, timing closure, and design optimization in close collaboration with our RTL, architecture, and external implementation partners. This is an exciting opportunity to contribute to cutting-edge silicon development that powers advanced AI systems at the edge.

The Team

As a team, we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium-form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy efficiency for AI inference at the edge.

About EdgeCortix

EdgeCortix is a deep-tech, fabless semiconductor startup revolutionizing edge computing with artificial intelligence and high-efficiency system-on-chip (SoC) design. Founded on years of advanced research, our proprietary hardware-software co-design methodology and Dynamic Neural Accelerator AI processor IP are reshaping the AI hardware space. Headquartered in Tokyo, Japan, we also operate in Singapore, the United States (California and Virginia), and India.

Your Role and Responsibilities

As a Physical Design Engineer, you will contribute to the implementation of our next-generation AI acceleration SoCs and chiplets. As part of small internal PD team,  you will be responsible for driving key aspects of the front-end synthesis experiments to determine optimal PPA operating point and taking the IPs through Place and Route flow through close collaboration with RTL design  and architecture teams. The sign-off  activities and regular P&R progress has to be closely collaborated with our external implementation partners.

This role emphasizes synthesis, timing analysis, floorplanning, power optimization, and design closure, with a strong focus on communication and coordination across internal and external teams.

Key Responsibilities

• Drive and maintain RTL-to-GDSII flow, focusing on synthesis, STA, and design closure. Knowledge of DVFS, MMMC is important
  
• Strong Synthesis knowledge essential. Able to conduct multiple experiments at Synthesis and take it to P&R and provide feedback to IP teams
• Define floorplans and block partitioning strategies for hierarchical designs.
  
• Coordinate with external vendors for backend P&R execution; review their outputs for quality and correctness.
  
• Analyze timing paths and lead STA closure across PVT corners and operating modes.
  
• Develop and optimize physical constraints (SDC, TCL) and run equivalence checks.
  
• Placement analysis, congestion analysis, Clock Tree implementation experience needed
  
• Evaluate standard cell libraries and implementation methodologies to improve PPA.
  
• Implement low-power design strategies using UPF (Unified Power Format).
  
• Review power grid planning and sign-off reports (IR-drop, EM).
  
• Drive ECO implementation based on RTL changes or timing requirements.
  
• Collaborate with internal RTL and architecture teams to improve logic and system-level PPA.
  
• Participate in early feasibility studies and contribute to PPA projections.
  
• Maintain and improve internal automation scripts and flows.
  
  

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
  
• 5+ years of experience in physical design of SoCs with a focus on synthesis and timing.
  
• Proficiency in STA and synthesis tools (e.g., Primetime, Design Compiler, Genus).
  
• Familiarity with backend flows and interaction with P&R teams (internal or external).
  
• Good scripting skills (TCL, Python, Shell).
  
• Experience working with advanced technology nodes ( 12nm and below).
  
  

Preferred Qualifications

• Master's degree in relevant field.
  
• 8–10+ years of experience in physical design or chip implementation.
  
• Prior experience coordinating with remote backend implementation teams.
  
• Experience in chiplet architecture or hierarchical SoC designs.
  
• Understanding of sign-off checks (LVS, DRC), IR-drop, crosstalk, and EM analysis.
  
• Proficiency in UPF-based low-power flows and ECO handling.
  
• Strong communication and project coordination skills.
  
  

What's in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Location

Hyderabad is the primary work location, Bangalore is also available.

Hybrid Remote working is allowed.

Benefits and Perks

• • Highly competitive salary and stock options
  • Flex work time
  • Top-tier employee benefits