Stagiaire Ingnieur Vrification Circuit Intgrs F/M

1 week ago

France, India NXP Semiconductors Full time € 40,000 - € 60,000 per year
Job Description

Locations
Toulouse

Time Type
Full time

Posted On
Posted Today

Job Requisition ID
R

Dploiement dune stratgie de vrification systme base sur DMS (Digital Mixed Signal) pour les circuits de gestion dalimentation

Contexte :
Au sein de NXP Toulouse, dans le cadre des activits de vrification digitale des circuits intgrs ddis la gestion dalimentation, ce stage vise dfinir et mettre en uvre une stratgie de vrification systme reposant sur une approche DMS.

Objectifs du stage :

  • Analyser le flow de vrification digitale actuel, ses outils, ses contraintes et ses points de friction.
  • Identifier et implmenter les volutions ncessaires pour intgrer une stratgie DMS adapte aux besoin.
  • valuer les bnfices et les limites de la stratgie DMS en termes de productivit, couverture et traabilit.
  • Dfinir et consolider le primtre de la vrification DMS dans le cadre de la vrification globale IC compose des quipes DV/AMS/AVT.
  • Appliquer la stratgie sur des fonctions standards telles que les blocs Powerup Management / LDO / ABIST.

Deployment of a System-Level Verification Strategy Based on DMS (Digital Mixed Signal) for Power Management ICs

Context:
At NXP Toulouse, within the digital verification group for power management integrated circuits, this internship aims to define and implement a system-level verification strategy based on a DMS (Digital Mixed Signal) approach.

Internship Objectives:

  • Analyze the current digital verification flow, including tools, constraints, and bottlenecks.
  • Identify and implement the necessary improvements to integrate a DMS-based strategy tailored to project needs.
  • Evaluate the benefits and limitations of the DMS strategy in terms of productivity, coverage, and traceability.
  • Define and consolidate the scope of DMS verification within the global IC verification framework, involving DV, AMS, and AVT teams.
  • Apply the strategy to standard functions such as Power-Up Management blocks, LDOs, and ABIST.

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