ASIC RTL Design Engineer

2 days ago


Bengaluru, Karnataka, India Evnek Full time ₹ 15,00,000 - ₹ 20,00,000 per year
  • Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs
  • Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications
  • Review micro-architecture and provide design solutions optimized for power, performance, and area
  • Work closely with the verification team to ensure thorough test coverage and efficient debugging
  • Collaborate with synthesis, STA, and physical design teams for design closure

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