Senior AMS Design Verification Engineer

3 days ago

Bengaluru, Karnataka, India Chiplogic Technologies Full time ₹ 12,00,000 - ₹ 24,00,000 per year

Company Description

Chiplogic Technologies, established in 2018, is a leading IP and Product Engineering Services company specializing in Semiconductor, Systems, IoT, and AI/ML areas. The company provides high-quality and dependable services, including full-turnkey semiconductor design, system solutions from concept to silicon, and IoT final system solutions. Leveraging its proprietary VISARD framework, Chiplogic delivers innovative solutions in AI/ML and video synthesis. Chiplogic is committed to driving technological excellence and enabling its clients to achieve transformative outcomes.

Job Description:

We are looking for an experienced
Analog Mixed-Signal (AMS) Design Verification Engineer
with a strong background in
PMICs, Analog IPs, or Mixed-Signal SoCs
. The ideal candidate will have hands-on experience in
Verilog-AMS, SystemVerilog, and mixed-signal co-simulation
, along with a deep understanding of
analog and digital design concepts
.

You will work closely with design, modeling, and validation teams to ensure the functional and behavioral correctness of complex mixed-signal systems.

Key Responsibilities:

  • Develop and execute
    AMS verification plans
    based on design specifications.
  • Create and maintain
    mixed-signal verification environments
    using
    Verilog-AMS
    ,
    SystemVerilog
    , and
    wreal modeling
    .
  • Perform
    co-simulation
    and
    behavioral modeling
    of analog blocks such as
    LDOs, DC-DC converters, bandgaps, ADCs/DACs
    , etc.
  • Collaborate with analog and digital design teams for
    top-level mixed-signal verification
    .
  • Debug simulation failures and drive coverage closure.
  • Automate test environments and regression flows using
    Python / Perl / TCL scripting
    .
  • Participate in methodology development and continuous improvement of AMS verification flows.

Required Skills & Experience:

  • 5+ years
    of experience in
    Analog Mixed-Signal Design Verification
    .
  • Proficiency in
    Verilog-AMS
    ,
    SystemVerilog
    , and
    mixed-signal simulation methodologies
    .
  • Experience with
    Cadence AMS Designer
    ,
    Synopsys VCS AMS
    , or
    Mentor Questa ADMS
    tools.
  • Strong understanding of
    analog circuits
    and
    digital verification flows
    .
  • Experience verifying
    PMICs
    ,
    Analog IPs
    , or
    Mixed-Signal SoCs
    .
  • Solid debugging and problem-solving skills in mixed-signal environments.
  • Scripting experience with
    Python / Perl / Shell / TCL
    for automation.

Preferred Qualifications:

  • Exposure to
    UVM-MS (Mixed-Signal UVM)
    or
    SystemVerilog Assertions (SVA)
    .
  • Knowledge of
    power management circuits
    (LDOs, DC-DC, bandgap, charge pumps).
  • Familiarity with
    post-silicon validation correlation
    .
  • Strong communication and collaboration skills across analog/digital teams.

Tools & Environment:

  • Simulation Tools:
    Cadence AMS Designer, Synopsys VCS AMS, Mentor Questa ADMS
  • Languages:
    Verilog-AMS, SystemVerilog, wreal
  • Scripting:
    Python, Perl, Shell, TCL
  • Version Control:
    Git, Perforce

Why Join Us:

  • Opportunity to work on
    cutting-edge Analog & Mixed-Signal products
    .
  • Collaborate with
    industry experts
    in AMS design and verification.
  • Competitive salary and a supportive, innovation-driven work environment.
  • Immediate joiners are highly preferred

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