Design Verification Engineer

2 weeks ago


Bengaluru Hyderabad Noida, India Silcosys Solutions Full time ₹ 20,00,000 - ₹ 25,00,000 per year
  • We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure.

Key Responsibilities:

  • Develop and maintain constrained-random and directed testbenches using System Verilog/UVM
  • Define verification plans and test strategies based on specifications
  • Write test cases, checkers, and functional coverage models
  • Perform RTL simulations, debug failures, and ensure coverage closure
  • Collaborate with RTL, DV, and firmware teams across verification lifecycle
  • Support gate-level simulation, regression management, and post-silicon bring-up

Requirements :

  • 8+ years of hands-on experience in digital design verification
  • Expertise in System Verilog, UVM, and verification methodology
  • Strong debugging skills using simulators like VCS, Questa, or Incisive
  • Good understanding of protocols like AMBA (AXI/AHB/APB), PCIe, Ethernet, etc.
  • Experience with coverage tools, version control, and regression systems
  • Strong communication, collaboration, and documentation skills


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