Asic - SOC Design Verification

22 hours ago

Bengaluru Karnataka, India Advanced Micro Devices Full time

**ASIC - SoC Design Verification**:

- Bangalore, India
- Engineering
- 64581

**Job Description**:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**
- We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
- AMD together we advance_

**SE**NIOR** SILICON DESIGN ENGINEER** (AECG ASIC - SoC Design Verification)

**THE ROLE**:

- The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design.

**THE PERSON**:

- You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

**KEY RESPONSIBILITIES**:

- Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks
- Ability to come with detailed testplan based on the Arch specs
- Good understanding and exposure to SoC design and architecture
- 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge
- Own the DV sign-off and ensure a bug free design
- Work with the post-silicon team on debug support and to help root-cause any failures
- Have worked on wireless protocol design verification
- Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow
- Exposure to DEBUG concepts such as JTAG etc
- Comfortable with VCS/Verdi and excellent debug skills
- Logical in thinking and ability to gel well within a team
- Good communication skills

**PREFERRED EXPERIENCE**:

- Proficient in SoC/sub-system/IP level ASIC verification
- Proficient in debugging RTL code using simulation tools
- Experienced with Verilog, System Verilog, C, and C++
- Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol
- Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification
- Developing UVM based verification frameworks and testbenches, processes and flows
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Python, Makefile, shell preferred.

LI-RP1

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