Sta (Static Timing Analysis) 4 to 6 Years Bengaluru

4 hours ago

Bengaluru, India Capgemini Engineering Full time

Experience in Synthesis of complex SoCs block/ top level and writing timing constraints.
- Experience in formal verification RTL to netlist - to
- netlist with DFT constraints.
- Experience in post-layout STA closure and timing ECOs.
- Worked in technology nodes 45 nm and below.
- Knowledge of low -power aware implementation is a plus.
- Tools: Design compiler, RTL compiler, LEC, CLP, ETS/ PTSI/ GT.

**Primary Skills**
- Able to handle Soc/Subsystem and block level synthesis activities, SoC/ Subsystm and block level LEC, CLP and timing closure.

**Secondary Skills**
- Able to handle PTPX and debug CTS issues to balance clocks.

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