
Cpu Verification
2 weeks ago
Overview:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
**Responsibilities**:
**SMTS SILICON DESIGN ENGINEER**
**T**HE ROLE**:
As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
**THE PERSON**:
**KEY RESPONSIBILITIES**:
- Deep understanding on X86 Architecture and Good knowledge on L2/L3 Cache micro architecture
- Developing complex assembly tests to cover required area of feature.
- Re-creating post silicon failures in in pre-silicon
- Debugging and fixing test cases in assembly language.
- System Verilog and CPP checkers to support new features
- Debug Skill, Debug triage of failures from simulation and emulation environment for CORE or sub-level regressions.
- Able to write complex perl program to update sim file in deterministic way.
- ** PREFERRED EXPERIENCE**:
- Minimum 12+ years’ experience in ASIC Design Verification, with knowledge of Computer Architecture, Cache levels
- Solid background and understanding of Digital Design, RTL design and strong troubleshooting, analytical and debugging skills.
- Must have excellent knowledge of design & verification flows and system knowledge.
- Excellent hands-on debug skills, excellent problem solving skills
- Post Si debugging is preferred.
- Any Verification methodology involving OOPs concepts C++, OVM/UVM methodology knowledge and experience is a plus.
- Prior experience in functional verification of Processor subsystems such as x86 or ARM domain-based Cores
- Excellent script writing (Perl)
**K**EY RESPONSIBLITIES**:
- Implementation and verification of DFT architecture and features
- Scan insertion and ATPG pattern generation
- ATPG patterns verification with gate-level simulation
- Test coverage and test cost reduction analysis
- Post silicon support to ensure successful bring up and enhance yield learning
**P**REFERRED EXPERIENCE**:
- Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
- Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
**ACADEMIC CREDENTIALS**:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
LI-ST1
Qualifications:
- Benefits offered are described: _AMD benefits at a glance.
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