St Asic Design Engr
2 weeks ago
In this role, you are expected to work with architects to understand the requirements, document them, get them reviewed, and implement the functional block or an IP.
What you will be doing:
- Work closely with Architects to understand the requirements, document them, and implement the functional block or an IP
- Work in capturing the design intent, uArch, RTL coding, API coding, lint, constraints development, CDC, and synthesis
- Debug the designs and work with verification team members to get their design block functionally completed
- Integrate blocks and create physical design blocks
- Work with the Physical Design team to ensure that the design meets area, timing, power requirements
- Opportunity to test their design block in the lab and work with lab validation team members
What we seek:
- Ability to abstract complex functions
- Ability to do the uArch using block diagrams, waveforms, and mathematical and logical models/equations
- Good understanding of the use of FIFOs, state machines
- Exposure to RTL coding using Verilog/System Verilog
- Good logic design skills with the ability to understand timing, area, and power reports
- Experience in timing constraints development, running lint and CDC checks, synthesis using ASIC or FPGA tools
- Interested in using assertions and formal property verification to develop bug-free designs
- Experience of 5+ years in design (uArch, RTL coding, RTL checks and debug)
- Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to_
- race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment._
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