Dft Design

1 week ago

Bengaluru, India Screenovate Full time

As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
- Your responsibility will also include verification and silicon bring up of Scan ATPG and other DFT features.
- In addition, you will help develop and deploy DFT methodologies for our next generation products.
- Working with soc/post silicon team to improve/ address low scan coverage and implement methodology to enhance scan coverage is expectation.
- Collaborate with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects.

**Qualifications**
- Experience in various aspects of DFT - SCAN insertion, ATPG, MBIST & JTAG, BSCAN. Test generation, coverage improvement, post-silicon debug.
- Well verse with OVM/UVM validation methodology on building Test bench to implement monitors, checkers, scoreboard.
- Hands on experience on DFT industry standard tools from Cadence, Mentor Graphics used for SCAN insertion, MBIST implementation and validation is must have requirement.

**Inside this Business Group**
Intel's Human Resources group is responsible for hiring, developing and retaining the best and brightest employees while continuing to strengthen the company's culture and values. Intel Human Resources provides first-rate, cost-effective services and support to employees worldwide and is dedicated to advancing Intel's business goals.

**Posting Statement**
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits

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