Asic Digital Design Engr, Staff

1 day ago

Bengaluru Karnataka, India Synopsys Full time

48093BR
- INDIA - Bangalore

**Job Description and Requirements**

**_ASIC Digital Design Engineer, Design Lead_**

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.- ASIC Digital Design/Verification Engineer, Senior_
- We’re looking for **_Senior ASIC Digital Design Engineer _**to join Synopsys Solutions Group, Digital IP Subsystems Team.
- Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs. _Join the Synopsys Subsystems Team _
Based in our offices in Bangalore/Hyderabad, India, you will be a senior member of the Synopsys Solutions Group Subsystems team, which is developing high performance Digital Interface IP Subsystem solutions for DDR, PCIe, Ethernet, UFS, USB and other interface protocols.
- In this role,
- As a_ _Lead Design Engineer_, you will be responsible for RTL Design, Architecting & Integrating the Subsystems, signing off on the front-end implementation flows, Work with Design and Verification teams driving the life-cycle of the Subsystems from requirement to release phases.

Requirements:

- Knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.
- Programming skills such as System Verilog, TCL, Perl or Python.
- The ability to work independently, precisely and to drive innovation
- The ability to extract detailed requirements from high-level specification
- Good communication skills.
- Lead Design Engineer position will require you to:_
- Understand the requirements and Architect the Subsystems based on the requirements.
- Integrate the RTL and drive the Design tasks to complete the Subsystem
- Sign-off on the front-end implementation flows like Synthesis timing closure using DC/Fusion Compiler, SpyGlass CDC/RDC checks, Low Power Architecture, Formality and others.
- Be part, and, lead the Verification closure by interacting with the Verification teams
- Drive the life-cycle of the Subsystems through various phases, from requirements to delivery.
- Key Qualifications for Design Engineers:_
- Hands-on/Lead experience on Subsystems/SOC Design, Architecture and Implementation.
- Experience with Verilog/System Verilog coding and simulation tools.
- Experience of implementation flows, namely: synthesis flow, lint, CDC, low power and others
- Please get in touch with us. Looking forward to talk to you
- Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability._

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

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