Pe Physical Design

Overview:
Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Physical engineer to join our Physical Design team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

**Responsibilities**:

- Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification,
- Take complete ownership for implementation of both Top/Block level designs.- Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 28nm nodes or below.
- Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM, Timing Closure, constraint (sdc) development)
- Well versed with the block and chip level timing closure (STA) and timing closure methodologies. Also need to have experience with constraints development. Experience in Hierarchical and Flat timing flow bring-up and timing analysis on interface paths. Block level/Fullchip/SOC level/Mixed signal timing path analysis and fixing.
- Must have knowledge of low power design. (cpf, upf CLP).
- Should be able to provide clear directions to the team on various implementation and signoff flows
- Should be well versed in LEC flow and debugging issues independently.
- Role involves tasks in estimating power using industry standard tool, designing power grid, analyze power grid, doing static IR drop, dynamic IR drop
- Role involves analyzing DRC, LVS,ERC and PERC rule files for industry standard layout verification.

Qualifications:
- Must have minimum Bachelors degree in EE/ECE (degree’s related to electronics) from a reputed institute.
- Must have at least 10 years of experience, out of which at least 8 years should be related to physical design at chip level / block level.
- Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
- Experience in Tcl/Tk, PERL is a Plus

**About Rambus**

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard.

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.