Asic Digital Design Engr, Staff

1 week ago

Bengaluru, India Synopsys Full time

41321BR
- INDIA - Bangalore, INDIA - Pune

**Job Description and Requirements**
- At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.- The role involves developing and working on design of high speed PHYs and Serdes. Additionally you will be involved in:
- Design architecture development and its review
- RTL design development
- Debug of simulations, including those of real signals modeled using SV for analog
- RTL, GLS, Co-simulations
- Deliver high quality RTL and other simulation models to customer
- Participate in technical reviews and contribute actively
- Participate in customer support with bring-up of IP in customer simulation environment
- Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest
- Follow and improve development process ensuring high quality output
- Skill Set- Hands on experience with HVL, or HDL like VHDL, System Verilog
- Knowledge of Perl/Shell scripts
- Knowledge of protocols like Ethernet, PCIe, other networking protocols

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

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