SOC Design Engg
1 week ago
Physical design engineer with experience in Structural Design. Hands-on experience of block, IP, and full-chip floor-planning, synthesis, APR, static-timing, electrical/reliability analysis, tapeout flows.Leading capability to drive SD improvements, definitions and execution. Good communication and team work skills. Knowledge of RTL-to-GDS flow through synthesis and P and R with targets for power, performance, and area. Implement and validate physical design on the aspects of timing, area, reliability, testability and power. Developing SD teams for optimal performance and productivity.Define area, frequency, performance, power and schedule trade-offs
**Qualifications**
**Inside this Business Group**
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
**Work Model for this Role**
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
**Legal Disclaimer**:
Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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