Asic Physical Design Engr Ii
4 days ago
46882BR
- INDIA - Bangalore, INDIA - Hyderabad
**Job Description and Requirements**
In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in close interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team.
- 5+ years of digital or physical design experience with recent contribution to project tape-outs
- Strong understanding of the full design cycle from RTL to GDSII, including chip level.
- Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
- A solid engineering understanding of the underlying concepts of digital design and architecture, implementation flows and physical and timing signoff
- Development of timing constraints and design architectures to ensure on-time delivery, and to meet or exceed power and area targets
- Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers
- Methodology driven with strong software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.
- Solid understanding of the challenges inherent in analog/digital interfaces.
- Proficient with place and route, synthesis and timing analysis tools - ICC2, Design Compiler, PrimeTime, Fusion Compiler
- Proficient with physical verification tools and flows - ICV, Calibre for LVS, DRC, ERC, PERC
**Requirements**:
- MSEE and 3+ years, BSEE and 5+ years
- Solid understanding of digital / mixed signal flows and SOC integration challenges
**Job Category**
- Engineering
**Country**
- India
**Job Subcategory**
- ASIC Physical Design
**Hire Type**
- Employee
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