Memory Layout

2 days ago

Bengaluru, India DTC Infotech Full time

**Experience**: 2+ Years

**Location**: Bangalore
Roles and Responsibilities
Memory leaf cell layout development
Migration of layout from one tech node to another
Block and top-level integration
Quality and timely delivery
EM-IR, area intensive layouts, Quality checks (QC)
Understanding of design rules for planer and FINFET CMOS technologies
Drive multiple projects and provide necessary technical guidance to the engineers
Experience in developing flash memories.
**Requirements**:
2+ Yrs of Memory Layout experience in development of low power, high performance, high density SRAM memories for 5nm to 180nm technology nodes
Expertise in Custom / Compiler Memory Layout
7nm or below FinFet technology preferred
Understanding of DFM and DFY checks.
Understanding of memory compiler architectures and sub blocks.
Knowledge of scripting in PERL/Shell/TCL/Skill is a plus.
Strong VLSI fundamentals of semiconductor devices and physics, electrical circuits and IC fabrication.

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