Physical Design 9 to 12 Years Bengaluru

1 week ago

Bengaluru, India Capgemini Engineering Full time

Must possess 9+ years of hands-on experience in handling block/chip level implementation from Netlist to GDS
- Must possess hands-on experience in timing closure and physical verification closure
- Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz.
- Experience in handling lower-tech nodes that include 40nm, 28nm, or lesser nodes etc.
- Must have hands-on tape-out experience in lower tech nodes in any of the tools mentioned such as ICC or SOC Encounter or mentor tools.
- Must have the ability to think on the spot for quick solutions and work-around at the time of tape out to hit the schedule on time.
- Must possess excellent scripting skills - TCL or Perl.
- Experience in Synthesis and Formal is a plus.
- Excellent verbal and written communication skills are required.
- Must possess excellent debug skills, analytical skills, and the ability to work independently.
- Must be highly motivated and possess excellent team spirit.

**Primary Skills**
- Ability to lead a team size of a minimum of 10 members who can handle Subsystem PNR activities, Subsystem timing closure, and Subsystem physical verification.

**Secondary Skills**
- Knowledge in Subsystem Synthesis, Subsystem IR drop, Subsystem Lec, Subsystem CLP.

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