Strategic / Leadership Role - Dft

3 days ago

Bengaluru Karnataka, India Advanced Micro Devices Full time

**Strategic / Leadership Role - DFT**:

- Bangalore, India
- Engineering
- 64595

**Job Description**:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**
- We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
- AMD together we advance_

**FELLOW**SILICON DESIGN ENGINEER** (DFT)

**THE ROLE**:

- We are looking for a Fellow-level Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define and implement the DFT Architecture, guide/technically lead the DFT Team to ensure right pre-si verification is done for the DFT logic, and the highest level of Scan coverage is achieved to hit the product goals. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction)

**THE PERSON**:

- You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities.

**KEY RESPONSIBILITIES**:

- Work closely with the SoC Architecture and uArch teams to define the DFT architecture.
- Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up
- Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up
- Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models
- Work with the post-silicon team on debug support and to help root-cause any failures
- Be upto date with the industry trends and bring-in the latest to the AMD products
- Work with DFT Tool Vendors and drive improvements based on our requirements

**REQUIREMENTS**:

- 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes.
- Good understanding and exposure to SoC design and architecture
- Very good understanding of verif and timing concepts having handled DFT timing closure
- Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc
- Comfortable with VCS/Verdi and Mentor TK.
- Logical in thinking and ability to gel well within a team
- Good stakeholder management
- Ability to quickly adapt to changes and handle pressure
- Good communication and leadership skills

**ACADEMIC CREDENTIALS**:

- Bachelors or Masters degree in Computer engineering/Electrical Engineering

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