Digital Design/verification Intern

7 days ago

Salt Lake Kolkata West Bengal, India Semifront Technologies Private Limited Full time

**Description : -**
Semifront is looking for folks who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad-level Microarchitecture and Architecture Specs.

**Skills and other requirements: -**
- 1. Excellent/good Verilog/SystemVerilog/Perl Skillset
- 2. The coding will be Perl mixed Verilog/SV
- 3. Knowledge of Make, Python, Bash is an advantage, but not mandatory
- 4. The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory
- 5. The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to detail and humility to learn from the right feedback.

**Who can apply: -**
- 1. Fresher/junior engineers looking for an opportunity.
- 2. People looking for training/upscaling in the domain can apply.
- 3. People looking to explore in-depth from scratch ASIC design can also apply.

**Benefits : -**
- 1. Opportunity to work in complex ASIC product design from scratch
- 2. Opportunity to learn alongside experienced and passionate engineers who have helped build IPs/SoCs from scratch
- 3. Monthly stipend/remuneration
- 4. Facility to work partially remotely for excellent individuals
- 5. Opportunity to convert to full-time engineers for excellent performing individuals

**Job Types**: Full-time, Fresher, Internship
Contract length: 6 months

**Salary**: ₹11,000.00 - ₹15,000.00 per month

**Benefits**:

- Flexible schedule
- Paid sick time

Schedule:

- Day shift
- Flexible shift

Supplemental pay types:

- Performance bonus

Ability to commute/relocate:

- Salt Lake, Kolkata - 700091, West Bengal: Reliably commute or planning to relocate before starting work (required)

Application Question(s):

- Please mention what is your expertise level in these languages in either of 3 categories - BEGINEER/INTERMEDIATE/EXPERT

Languages are : - Verilog, SystemVerilog, UVM, Perl, Bash, Make
- Do you have experience working in Linux or Unix Environment ?

**Education**:

- Bachelor's (preferred)

**Experience**:

- total work: 1 year (preferred)

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