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AMS Verification
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AMS Verification
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Bengaluru, India UST Full timeHi,Looking for AMS Verification Lead, 3 to 8+ yrs3 to 8+ years of experience in AMS verification for semiconductor design.Expertise in Verilog-A/Verilog AMS for modelling analog/mixed-signal components.Proficiency with Xcelium (Cadence) or similar simulation and verification tools.Strong understanding of analog design concepts (e.g., PLLs, ADCs, DACs,...
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AMS Verification Engineer
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Bengaluru, Karnataka, India eInfochips (An Arrow Company) Full timeJob Title: AMS Verification EngineerExperience Required: Minimum 4 years relevant experience is required.Location: Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, PuneKey Responsibilities:- Min 4 Years of overall experience in ASIC Verification- Should have worked on AMS Verification for minimum of 2 years- Develop and execute verification plans for AMS...
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AMS Verification Engineer
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Bengaluru, Karnataka, India eInfochips (An Arrow Company) Full timeJob DescriptionJob Title: AMS Verification EngineerExperience Required: Minimum 4 years relevant experience is required.Location: Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, PuneKey Responsibilities:- Min 4 Years of overall experience in ASIC Verification- Should have worked on AMS Verification for minimum of 2 years- Develop and execute verification...
Ams Design Verification
2 weeks ago
**Job Overview**
**Analog Mixed Signal Design Verification**
**(INDIA) BANGALORE, INDIA /**
**ENGINEERING - SILICON ENGINEERING /**
**FULL-TIME**
Join a well-funded hardware start up as an AMS DV engineer leading the design verification for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs.
**Responsibilities**
- Responsible for performing verification for AMS designs.
- Create UVM benches for mixed signal blocks and developing test scenarios.
- Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage
- Write assertions and checkers for the properties and corner cases
- Analyze verification coverage and improve the test cases
- Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation
**Requirements**:
- Detailed knowledge of verification using SystemVerilog
- Experience with assertion based verification for analog blocks
- Experience with power aware verification with UPF will be a plus
- UVM-AMS experience preferred
- Experience with sv-real preferred
- Scripting skills in perl / python is preferred
- Excellent communication skills
- Team player with an ability to encourage team members
**Education & Experience**
MS (preferred in EE and CE) plus 5 years
**Salary**: ₹910,000.00 - ₹1,070,000.00 per year
**Benefits**:
- Health insurance
- Provident Fund
Schedule:
- Day shift
- Flexible shift
- Monday to Friday
- Health insurance
