Sta Fxte/subcon
3 days ago
**Skills**:
Experience in Synthesis of complex SoCs block/ top level and writing timing constraints.
Experience in formal verification RTL to netlist - to
- netlist with DFT constraints.
Experience in post-layout STA closure and timing ECOs.
Worked in technology nodes 45 nm and below.
Knowledge of low -power aware implementation is a plus.
**Tools**: Design compiler, RTL compiler, LEC, CLP, ETS/ PTSI/ GT.
**Primary Skills**:
Able to handle Soc/Subsystem and blocklevel synthesis activities, Soc/Subsystem and blocklevel LEC, CLP and timing closure
**Secondary Skills**:
Able to handle PTPX and debug CTS issues to balance clocks
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Sta Fxte/subcon
3 days ago
Noida, India Response Informatics Full timeExperience in Synthesis of complex SoCs block/ top level and writing timing constraints. Experience in formal verification RTL to netlist - to - netlist with DFT constraints. Experience in post-layout STA closure and timing ECOs. Worked in technology nodes 45 nm and below. Knowledge of low -power aware implementation is a plus. **Tools**: Design...
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Pd Fxte/subcon
3 days ago
Noida, India Response Informatics Full timeManage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with front-end...
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Pd Fxte/subcon
3 days ago
Noida, India Response Informatics Full time**Senior Manager - Physical Design** **Description**: Manage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the...
