Chassis Power Architect, Device and Services

**Minimum qualifications**:

- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in power optimization workflow and techniques.
- Experience with power management IPs.

**Preferred qualifications**:

- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
- Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models.
- Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
- Experience in post-silicon power calibrations and debug.
- Experience in design and analysis of full chip power with an understanding of clock, reset, and power sequencing interactions.

**About the job**:
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the Google Silicon Platform IP Architecture team, you will collaborate with SoC and IP hardware architects and design engineers to drive next generation power management controller and chassis power optimization in advanced technology nodes, focused on Google Tensor SoC and other associated products.

In this role, you will define power management controller and it’s deployment across SoC, power optimization methods, chart power roadmaps for Chassis IPs, propose power optimization plans in consultation with cross-functional teams, guide pre-silicon power modeling and post-silicon power correlation efforts, and interface with system and chipset power architects on both power planning and power management strategies. Your primary focus will be on our next-generation power management controller, chassis power architecture/microarchitecture and power vs performance tradeoffs for various SoC and chassis components.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

**Responsibilities**:

- Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment.
- Come up with Power optimization methods for various chassis IP’s.
- Influence Power methodology for design, verification and implementation of deep submicron SoCs.
- Develop innovative schemes to achieve power optimization from circuit to system level.
- Influence generic power management IPs to drive clock, reset, and power controls.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.