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bangalore, India Angel and Genie Full timeRole- RTL DesignLocation- BangaloreExperience- 4to15 yearsJob Summary:We are looking for talented RTL Engineers and Leads with expertise in High-speed IPs and CPUs. The ideal candidate will have over 4 years and above experience in uArch design, RTL coding, quality checks (Linting, CDC, Synthesis) and integration of High-speed IPs/CPUs in complex ASICs/SoC...
Lead cpu rtl design engineer
1 month ago
Lead CPU RTL Design Engineer Ventana Micro Systems is at the forefront of the two hottest trends that are revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture.
Check out our CEO talking with global tech analyst Patrick Moorhead about how Ventana combines the extensibility of RISC-V with chiplet technology to create customer-driven innovation for best-in-class solutions for the data center.
Ventana is well-funded and backed by some of the largest strategic investors in the industry with the goal of building best-in-class CPU cores for cloud, enterprise, 5 G, and Edge computing.
We invite you to join the revolution and contribute to one of the Hottest Semiconductor startups in the industry.
Lead RTL Design Engineer: We are seeking an experienced design engineer to lead development of complex IP subsystems based on the open-source RISC-V architecture.
The right candidate will have deep technical expertise combined with exceptional leadership skills.
Responsibilities: Lead microarchitecture and RTL design of complex IP subsystems partnering with architecture teams Support verification and physical design teams to deliver high quality subsystems meeting appropriate PPA targets Mentor junior engineers to build a high performing team Minimum Qualifications: Bachelors or Masters degree in electrical, computer engineering or related field BS+8 years or MS+6 years of industry experience successfully delivering complex IP subsystems Skills & Qualifications Required: Demonstrated experience in developing microarchitecture from the ground up for complex IP blocks and delivering high quality designs Deep experience in RTL development in System Verilog / Verilog Well versed in industry standard RTL quality check methodologies such as lint and CDC checks Strong background in industry standards and protocols such as PCIe, Ethernet, CXL, AMBA AXI etc., Demonstrated team leadership experience with outstanding communication skills Highly motivated self-starter with strong execution mindset and collaborative approach Post-silicon debug experience strongly preferred Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
