Analog layout engineer

16 hours ago

Bangalore, India Eximietas Design Full time

We are seeking a highly skilled Analog Mixed Signal (AMS) Engineer with experience in advanced CMOS technology to join our team working on the 3nm process node for our esteemed client. The ideal candidate will have a strong background in AMS design and verification, with a particular focus on state-of-the-art fabrication technologies. Key Responsibilities: Excellent in doing layouts of any of the critical blocks like SERDES, LVDS, LDO, DAC, ADC, Oscillators, Comparators, Operational Amplifiers etc with good layout quality for TSMC/Samsung/Intel 3nm technology. ● Collaborate closely with digital design teams to integrate AMS circuits within larger So C designs ● Excellent understanding of CMOS / Bi-CMOS / SOI / Fin FET process. ● Excellent understanding of layout concepts like Latchup, Matching, Shielding, ESD, ● Electromigration, IR and Antenna, WPE, STI, LOD ● Extensive problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. Strong debug and problem solving skills in DRC, LVS, ERC, DFM, Density, EM, IR drop, Antenna Issues etc. Perform layout review, parasitic extraction, and post-layout simulations to ensure the performance and reliability of the designs. ● Participate in the tapeout process, ensuring successful first-pass silicon and providing support for post-silicon validation and debugging. ● Optimize circuits for power, performance, and area (PPA) in advanced CMOS nodes. ● Mentor junior engineers and provide technical guidance as needed. Preferred Qualifications: ● Bachelor’s or Master’s degree in Electrical Engineering or a related field. ● 4-7 years of industry experience in analog and mixed-signal circuit design. Experience with TSMC/Samsung/Intel 3nm process node and familiarity with high-speed interface design. Knowledge of power management circuits including LDOs, bandgap references, and DC-DC converters. ● Expertise in Matching, Shielding, Noise isolation, ESD, WPE, STI, LOD Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as Power, Performance and Area ● Proficiency of using Industry standard tools like Cadence Virtuoso XL, Synopsys IC compiler and Verification tools like Calibre and IC Validator ● Solid understanding of layout design principles, design rules, and process technologies. ● Knowledge of layout parasitic extraction and simulation techniques. ● Add-on Experience of Scripting knowledge like PERL, TCL is a plus

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