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Senior Engineer, Design Verification Engineering
2 weeks ago
Client is seeking a Design Verification Engineer. The role is technical, hands-on, in charge of the verification environment for new silicon projects and developments. We are looking for an experienced professional with Passion & Drive to succeed.
Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.
Design Verification – Implement test benches in UVM and Sytem
Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
Dynamic Power Management at full system level.
Work closely with Socionext's design team to ensure the Company is meeting design requirements for projects.
Work closely with Socionext's Custom SoC department to provide great customer service to our clients and the projects at hand. BS or MS in Computer Science or Electrical Engineering.
~5-10+ years of industry experience bringing silicon ICs into high volume production.
~ Must have strong experience with UVM.
~ Must have a full chip verification experience
~ Experience of leading a single project.
~ Expertise in writing Perl / Python, awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI,
~ Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
~ Experience with low-level programming of systems in C/C++.
~ Experienced in writing scripts in languages such as Perl, Python, and Tcl.
~ Experience with formal verification tools is a plus.
Familiarity with scripting/programming with Perl/Python, Tcl, C/C++
